Semiconductor device and method for fabricating the same

ABSTRACT

A semiconductor device of this invention includes a first interconnect pattern formed on a semiconductor substrate and a second interconnect pattern formed above the first interconnect pattern with an interlayer insulating film sandwiched therebetween. The first interconnect pattern includes a dummy pattern insulated from the first interconnect pattern, and the dummy pattern includes a plurality of fine patterns adjacent to each other and air gaps formed between the adjacent fine patterns.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a semiconductor device having amulti-level interconnect structure, and more particularly, it relates toa semiconductor device including a dummy pattern useful in planarizationof an interlayer insulating film formed on an interconnect pattern and amethod for fabricating the same.

[0002] Recently, in accordance with improvement in integration andperformance of semiconductor devices, interconnect patterns included ina device are refined and formed in multiple levels. Owing to therefinement and the multi-level structure of the interconnect patterns, alevel difference caused on the top face of an interlayer insulating filmhas become large and abrupt, which degrades the processing accuracy andthe reliability of the interconnect patterns.

[0003] In particular, a difference in the height (absolute height)between the top face of a wafer and the top face of an interlayerinsulating film, namely, the so-called global level difference, isincreased due to the multi-level structure of metal interconnects.Furthermore, since exposing light of a shorter wavelength is employed inthe lithography as the device is more refined, the depth of focusbecomes insufficient. As a result, the processing accuracy and thereliability of the interconnect patterns are degraded. As aplanarization technique for an interlayer insulating film for reducingthe global level difference, chemical mechanical polishing (CMP) isemployed.

[0004] Furthermore, the refinement and the multi-level structure of theinterconnect patterns in accordance with the increase in integrationlevel of semiconductor devices can increase capacitance betweeninterconnects. The increase of the capacitance between interconnectsaffects the operation speed of the semiconductor device, and hence, thecapacitance between interconnects needs to be reduced. In order toreduce the capacitance between interconnects, an insulating materialwith a low dielectric constant is used, and in order to further reducethe capacitance between interconnects, an air gap interconnect structurewhere air gaps are provided between interconnect patterns are employed.

[0005] The air gap interconnect structure is reported in, for example,papers written by T. Ueda et al. (A Novel Air Gap Integration Scheme forMulti-level Interconnects using Self-aligned Via Plugs: 1988 Symposiumon VLSI Technology Digest of Technical Papers, P. 46, 1998; andIntegration of 3 Level Air Gap Interconnect for Sub-quarter Micron CMOS:1999 Symposium on VLSI Technology Digest of Technical Papers, P. 111,1999).

[0006] Also in the formation of air gap multi-level interconnects, it isnecessary to planarize an interlayer insulating film. In theplanarization by the CMP, a dummy pattern is disposed in a portion whereinterconnect patterns are relatively sparse.

[0007] A conventional semiconductor device having the an air gapinterconnect structure including a dummy pattern used for theplanarization of an interlayer insulating film will now be describedwith reference to accompanying drawings.

[0008]FIGS. 7A through 7C and 8A through 8C are cross-sectional viewsfor showing procedures in a method for fabricating the conventionalsemiconductor device including an air gap interconnect pattern and adummy pattern.

[0009] First, as shown in FIG. 7A, a first insulating film 102 ofsilicon oxide, a conducting film 103 of aluminum alloy and a secondinsulating film 104 of silicon oxide are successively deposited on asemiconductor substrate 101 of silicon. Subsequently, a contact hole 104a for exposing the conducting film 103 is selectively formed in thesecond insulating film 104.

[0010] Next, as shown in FIG. 7B, the contact hole 104 a is filled withtungsten, thereby forming a plug 105.

[0011] Then, as shown in FIG. 7C, the second insulating film 104 isetched back so as to expose an upper portion of the plug 105. Theposition of the top of an air gap subsequently formed in theinterconnect pattern is determined by controlling the thickness of thesecond insulating film 104 remaining after the etch back.

[0012] Subsequently, as shown in FIG. 8A, a resist pattern 121A for afirst interconnect pattern and a resist pattern 121B for a dummy patternare formed on the second insulating film 104. With the resist patterns121A and 121B and the plug 105 used as a mask, the second insulatingfilm 104, the conducting film 103 and the first insulating film 102 aresuccessively etched, thereby forming, from the conducting film 103, afirst interconnect pattern 103 a and a dummy pattern 103 b having asquare plane shape. At this point, a portion of the first insulatingfilm 102 sandwiched between patterns of the first interconnect pattern103 a is trenched by the etching. Accordingly, an air gap can be easilyformed from a space between the patterns and the position of the air gapfrom the substrate surface can be adjusted.

[0013] Next, as shown in FIG. 8B, after removing the resist patterns121A and 121B, a third insulating film 107 of silicon oxide with lowcoverage and high directivity is deposited on the entire surface of thesemiconductor substrate 101. Thereafter, a fourth insulating film 108 ofsilicon oxide with high coverage is formed. At this point, an air gap122 is formed between the patterns of the first interconnect pattern 103a. Thus, the air gap interconnect structure is obtained.

[0014] Then, as shown in FIG. 8C, the top face of the fourth insulatingfilm 108 is polished and planarized by the CMP until the top face of theplug 105 is exposed.

[0015] In the fabrication method for the conventional semiconductordevice, however, although the dummy pattern 103 b is formed in a regionwhere the first interconnect pattern 103 a is relatively sparse on thesemiconductor substrate 101, a difference h1 in the absolute height ofthe top face of the fourth insulating film 108 between a portion abovethe first interconnect pattern 103 a and a portion above the dummypattern 103 b cannot be sufficiently small as shown in FIG. 8B.Therefore, even though the fourth insulating film 108 is planarized,there remains a difference h2 in the absolute height as shown in FIG.8C. Thus, a sufficiently planar face cannot be attained.

[0016] When a second interconnect pattern is formed on the fourthinsulating film 108 with such a difference h2 remaining, interconnectsincluded in the second interconnect pattern may be disconnected due tothe difference h2 or may fail due to high resistance. In order to moresufficiently planarize the top face of the fourth insulating film 108, alarger number of dummy patterns 103 b may be provided. When a largernumber of dummy patterns 103 b are provided, however, capacitancebetween interconnect layers and between interconnects become so largethat it is difficult to attain high operation speed. Therefore, thenumber of dummy patterns 103 b is not preferably increased.

SUMMARY OF THE INVENTION

[0017] The invention was devised to overcome the aforementionedconventional problems, and an object is reducing a difference in theabsolute height caused on the top face of an interlayer insulating filmafter planarization with the increase of capacitance betweeninterconnect layers and between interconnects suppressed.

[0018] The present inventors have variously studied the reason why thedifference h1 in the absolute height shown in FIG. 8B cannot be reducedto an allowable value in the conventional semiconductor device includingthe dummy pattern provided in a region where air gap interconnects arecomparatively sparse, resulting in finding out the following cause:

[0019] In the air gap interconnect structure, since the air gap 122 isprovided between the patterns of the first interconnect pattern 103 a,the absolute height of a region where the first interconnect pattern 103a is relatively dense is larger than the absolute height of aninterconnect pattern including no air gap. Accordingly, even though thedummy pattern 103 b is formed in the region where the first interconnectpattern 103 a is relatively sparse, the difference h1 in the absoluteheight from the portion above the dummy pattern is larger than that inthe interconnect pattern including no air gap.

[0020] According to the invention, in order to reduce the difference h1in the absolute height, a dummy pattern is formed as a plurality of finepatterns adjacent to each other with a space therebetween and the spaceis filled with nothing to form an air gap.

[0021] Specifically, the semiconductor device of this inventioncomprises a first interconnect pattern formed on a semiconductorsubstrate; and a second interconnect pattern formed above the firstinterconnect pattern with an interlayer insulating film sandwichedtherebetween, and the first interconnect pattern includes a dummypattern electrically insulated from the first interconnect pattern, andthe dummy pattern includes a plurality of fine patterns adjacent to eachother and air gaps sandwiched between the adjacent fine patterns.

[0022] In the semiconductor device of the invention, although the firstinterconnect pattern has the air gap interconnect structure where airgaps are formed between interconnect patterns, the absolute height ofthe top face of the interlayer insulating film in a portion above thedummy pattern is larger than that obtained without forming air gaps, andhence, a difference in the absolute height of the interlayer insulatingfilm from a portion above the first interconnect pattern can besufficiently small. Accordingly, even though the first interconnectpattern has the air gap structure, it can be sufficiently planarized bypolishing, so that a good second interconnect pattern can be definitelyformed on the sufficiently planarized interlayer insulating film withoutcausing a defect such as disconnection. Moreover, since the dummypattern itself has the air gap structure, the increase of thecapacitance between interconnects and between interconnect layers due tothe dummy pattern can be suppressed. Furthermore, when the dummy patternof this invention is provided so as to attain capacitance betweeninterconnect layers and between interconnects equivalent to thoseattained by a dummy pattern including no air gaps, a larger number ofdummy patterns can be disposed in a region where the first interconnectpattern is comparative sparse. As a result, the interlayer insulatingfilm can attain a further planar face.

[0023] In the semiconductor device, air gaps are preferably providedbetween adjacent patterns of the first interconnect pattern.

[0024] In the semiconductor device, the dummy pattern is preferablyformed in a region on the semiconductor substrate where the firstinterconnect pattern is relatively sparse.

[0025] The first method for fabricating a semiconductor device of thisinvention comprises a first step of forming a first interconnect patternforming layer from a conducting film on a semiconductor substrate and afirst insulating film on the first interconnect pattern forming layer; asecond step of forming a plug electrically connected to the firstinterconnect pattern forming layer by forming an opening in the firstinsulating film by selective etching and filling the opening with aconducting film; a third step of forming a resist pattern correspondingto a first interconnect pattern including a dummy pattern from a resistfilm applied over the semiconductor substrate including the plug; afourth step of patterning the first insulating film by etching the firstinsulating film with the resist pattern and the plug used as a mask; afifth step of forming, from the first interconnect pattern forminglayer, the first interconnect pattern and the dummy pattern that iselectrically insulated from the first interconnect pattern and includesa plurality of fine patterns adjacent to each other by etching the firstinterconnect pattern forming layer with the resist pattern and the plugused as a mask; a sixth step of forming, on the semiconductor substrate,a second insulating film covering the plug, the first interconnectpattern and the dummy pattern so as to form air gaps between patterns ofthe first interconnect pattern and between the fine patterns of thedummy pattern; and a seventh step of planarizing a top face of thesecond insulating film until the plug is exposed and forming, on thesecond insulating film, a second interconnect pattern electricallyconnected to the plug after planarization.

[0026] In the first method for fabricating a semiconductor device, thefirst interconnect pattern and the dummy pattern that is electricallyinsulated from the first interconnect pattern and includes a pluralityof fine patterns adjacent to each other are formed from the firstinterconnect pattern forming layer, and thereafter, the secondinsulating film is formed so as to form air gaps between patterns of thefirst interconnect pattern and the fine patterns of the dummy pattern.Accordingly, a difference in the absolute height of the top face of thesecond insulating film between a portion above the dummy pattern and aportion above the first interconnect pattern can be sufficiently small.As a result, the difference in the absolute height is sufficiently smalleven after the planarization of the second insulating film, and hence,no failure is caused in the second interconnect pattern formed on thesecond insulating film sufficiently planarized. Furthermore, since thedummy pattern itself includes the air gaps, the increase of thecapacitance between interconnects and between interconnect layers due tothe dummy pattern can be suppressed.

[0027] In the method for fabricating a semiconductor device, the firststep preferably includes a sub-step of forming an underlying insulatingfilm on the semiconductor substrate before forming the firstinterconnect pattern forming layer, and the method preferably furtherincludes, between the fifth step and the sixth step, a step of trenchingan upper portion of the underlying insulating film by etching theunderlying insulating film with the resist pattern and the plug used asa mask. In this manner, each space between the patterns of the firstinterconnect pattern and between the fine patterns of the dummy patterncan attain a high aspect ratio, and hence, the air gaps can be easilyformed between the patterns in the sixth step. Furthermore, the positionfrom the semiconductor substrate (height) of the air gap can be thuscontrolled.

[0028] The second method for fabricating a semiconductor device of thisinvention comprises a first step of forming a first interconnect patternforming layer of a conducting film on a semiconductor substrate; asecond step of forming a resist pattern corresponding to a firstinterconnect pattern including a dummy pattern from a resist filmapplied over the semiconductor substrate; a third step of forming, fromthe first interconnect pattern forming layer, the first interconnectpattern and the dummy pattern that is electrically insulated from thefirst interconnect pattern and includes a plurality of fine patternsadjacent to each other by etching the first interconnect pattern forminglayer with the resist pattern used as a mask; a fourth step of forming,on the semiconductor substrate, an insulating film covering the firstinterconnect pattern and the dummy pattern so as to form air gapsbetween the fine patterns of the dummy pattern; a fifth step ofplanarizing a top face of the insulating film and forming a plugelectrically connected to the first interconnect pattern by forming anopening in the insulating film after planarization by selective etchingand filling the opening with a conducting film; and a sixth step offorming, on the insulating film, a second interconnect patternelectrically connected to the plug.

[0029] In the second method for fabricating a semiconductor device, thefirst interconnect pattern and the dummy pattern that is electricallyinsulated from the first interconnect pattern and includes a pluralityof fine patterns adjacent to each other are formed from the firstinterconnect pattern forming layer, and thereafter, the insulating filmis formed so as to form air gaps between the fine patterns of the dummypattern. Therefore, a difference in the absolute height of the top faceof the insulating film between a portion above the dummy pattern and aportion above the first interconnect pattern can be sufficiently small.As a result, the difference in the absolute height can be sufficientlysmall even after the planarization of the insulating film, and hence, nofailure is caused in the second interconnect pattern formed on theinsulating film sufficiently planarized. In addition, since the dummypattern itself includes the air gaps, the increase of the capacitancebetween interconnects and between interconnect layers due to the dummypattern can be suppressed.

BRIEF DESCRIPTION OF THE DRAWINGS

[0030]FIGS. 1A and 1B are diagrams of a mask used in fabrication of asemiconductor device according to Embodiment 1 of the invention, whereinFIG. 1A is a plane view of an interconnect pattern and a dummy patternand FIG. 1B is an enlarged plane view of the dummy pattern;

[0031]FIGS. 2A, 2B, 2C and 2D are cross-sectional views for showingprocedures in a method for fabricating the semiconductor device ofEmbodiment 1;

[0032]FIGS. 3A, 3B and 3C are cross-sectional views for showing otherprocedures in the method for fabricating the semiconductor device ofEmbodiment 1;

[0033]FIGS. 4A, 4B and 4C are cross-sectional views for showingprocedures in a method for fabricating a semiconductor device accordingto Embodiment 2 of the invention;

[0034]FIGS. 5A, 5B and 5C are cross-sectional views for showing otherprocedures in the method for fabricating a semiconductor device ofEmbodiment 2;

[0035]FIGS. 6A, 6B and 6C are cross-sectional views for showing stillother procedures in the method for fabricating a semiconductor device ofEmbodiment 2;

[0036]FIGS. 7A, 7B and 7C are cross-sectional views for showingprocedures in a method for fabricating a conventional semiconductordevice including an air gap interconnect pattern and a dummy pattern;and

[0037]FIGS. 8A, 8B and 8C are cross-sectional views for showing otherprocedures in the method for fabricating the conventional semiconductordevice including an air gap interconnect pattern and a dummy pattern.

DETAILED DESCRIPTION OF THE INVENTION

[0038] Embodiment 1

[0039] Embodiment 1 of the invention will now be described withreference to the accompanying drawings.

[0040]FIGS. 1A and 1B show a mask used in fabrication of a semiconductordevice according to Embodiment 1 of the invention, wherein FIG. 1A is aplane view of an interconnect pattern and a dummy pattern and FIG. 1B isan enlarged plane view of the dummy pattern.

[0041] As shown in FIG. 1A, the interconnect pattern 10 included in themask 1 consists of an interconnect part 20 and dummy patterns 30disposed in a region where patterns of the interconnect part 20 arecomparatively sparse. The respective dummy patterns 30 are arranged, forexample, at spacing of 8.0 μm and a pitch of 10.0 μm.

[0042] As shown in FIG. 1B, the dummy pattern 30 includes threestripe-shaped fine patterns 30 a each with a length of approximately 2.0μm and a width of approximately 0.4 μm, and the three fine patterns 30 aarranged at spacing 30 b of approximately 0.4 μm between their longersides are disposed so as to have a plane outline in a square shape ofapproximately 2.0 μm×2.0 μm. The plane outline of each dummy pattern 30is a square in this embodiment, which does not limit the invention.Although each dummy pattern 30 includes the three fine patterns 30 a,the number of fine patterns 30 a is not limited to three but may be twoor more.

[0043] A method for fabricating a semiconductor device by using the mask1 having the aforementioned interconnect pattern 10 will now bedescribed with reference to the accompanying drawings.

[0044]FIGS. 2A through 2D and 3A through 3C are cross-sectional viewsfor showing procedures in the method for fabricating a semiconductordevice having an air gap interconnect structure and including a dummypattern according to this embodiment.

[0045] First, as shown in FIG. 2A, an underlying insulating film 52 ofsilicon oxide is deposited all over an interconnect region on asemiconductor substrate 51 of silicon by, for example, plasma CVD.Thereafter, a first interconnect pattern forming layer 53 of aluminumalloy is deposited all over the underlying insulating film 52 by, forexample, sputtering. Subsequently, a first insulating film 54 of, forexample, silicon oxide is deposited on the first interconnect patternforming layer 53. Then, a resist film (not shown) is applied on thefirst insulating film 54, thereby forming a mask pattern for a plug byphotolithography. The first insulating film 54 is etched by using thethus formed mask pattern, thereby forming a contact hole 54 a in thefirst insulating film 54.

[0046] Next, as shown in FIG. 2B, a conducting film of, for example,tungsten is deposited all over the first insulating film 54 includingthe contact hole 54 a by vapor deposition or the like, so as to fill thecontact hole 54 a with the deposited conducting film. Subsequently, anexcessive portion of the conducting film deposited on the firstinsulating film 54 is polished and removed by CMP, thereby forming aplug 55 of tungsten in the contact hole 54 a.

[0047] Then, as shown in FIG. 2C, the first insulating film 54 is etchedback so that at least an upper portion of the plug 55 can be exposed.The position of the top of an air gap subsequently formed in aninterconnect pattern can be determined by controlling the thickness ofthe first insulating film 54 remaining after the etch back.

[0048] Next, as shown in FIG. 2D, a resist pattern 71A for a firstinterconnect pattern and a resist pattern 71B for a dummy pattern areformed on the first insulating film 54. By using the resist pattern 71Afor a first interconnect pattern and the resist pattern 71B for a dummypattern as a mask, the first insulating film 54, the first interconnectpattern forming layer 53 and the underlying insulating film 52 aresuccessively etched. Thus, a first interconnect pattern 53 a includingspaces 53 c between adjacent patterns and a dummy pattern 53 belectrically insulated from the first interconnect pattern 53 a andincluding three fine patterns each having a stripe plane shape andspaces 53 d between adjacent fine patterns are formed from the firstinterconnect pattern forming layer 53. At this point, portions of theunderlying insulating film 52 exposed in the spaces 53 c and 53 d of thefirst interconnect pattern 53 a and the dummy pattern 53 b are trenchedby the etching. Therefore, the space 53 c of the first interconnectpattern 53 a also attains a high aspect ratio and the space 53 d of thedummy pattern 53 b originally has a high aspect ratio. As a result, airgaps can be easily formed in the spaces 53 c in a subsequent procedureand the positions of the air gaps from the substrate surface can beoptimized.

[0049] Furthermore, since a portion of the underlying insulating film 52below the side faces of the first interconnect pattern 53 a is removed,a lower fringe component of capacitance between adjacent interconnectscan be lowered.

[0050] Subsequently, as shown in FIG. 3A, after removing the resistpatterns 71A and 71B, a second insulating film 57 of silicon oxide forforming air gaps is deposited all over the semiconductor substrate 51including the plug 55, the first interconnect pattern 53 a and the dummypattern 53 b by plasma CVD using a monosilane (SiH₄) gas and adinitrogen monoxide (N₂O) gas. At this point, the second insulating film57 is preferably formed from a film with low coverage and highdirectivity. When such an insulating film with low coverage is used, thedeposited second insulating film 57 overhangs like a peak on the topportions of the adjacent patterns, and hence, an air gap can bedefinitely formed between the patterns. Thereafter, a third insulatingfilm 58, which may have high coverage, of silicon oxide to be used as aninterlayer insulating film is deposited all over the second insulatingfilm 57 by, for example, high density plasma CVD. As a result, air gaps72 are formed between the patterns of the first interconnect pattern 53a so as to attain the air gap interconnect structure, and air gaps 73are also formed between the fine patterns of the dummy pattern 53 b sothat the dummy pattern 53 b can also attain the air gap structure.

[0051] Also in this embodiment, there is a difference H1 in the absoluteheight of the top face of the third insulating film 58 between a portionabove the first interconnect pattern 53 a and a portion above the dummypattern 53 b. However, since the dummy pattern 53 b includes a pluralityof fine patterns and the spaces 53 d are formed between the adjacentfine patterns, a portion of the third insulating film 58 not filled inthe spaces 53 d rises in the portion above the dummy pattern 53 b, andhence, the absolute height of the portion above the dummy pattern 53 bis larger than that obtained without employing the air gap structure.The difference H1 is smaller than the difference h1 obtained by theconventional dummy pattern 103 b shown in FIG. 8B, and hence, thedeposited third insulating film 58 is superior in the planeness on itstop face.

[0052] Next, as shown in FIG. 3B, the top face of the third insulatingfilm 58 is polished and planarized by the CMP until the top face of theplug 55 is exposed. At this point, since the difference H1 in theabsolute height is sufficiently allowably small, a difference H2 in theabsolute height attained after the planarization is very small. Thus, asufficiently planar face can be obtained.

[0053] Then, as shown in FIG. 3C, a conducting film electricallyconnected to the plug 55 is formed on the planarized third insulatingfilm 58 by the sputtering or the like, and a second interconnect pattern59 is formed from the conducting film. At this point, since the thirdinsulating film 58 is sufficiently planarized, the second interconnectpattern 59 is never disconnected owing to the level difference of thethird insulating film 58. Accordingly, the second interconnect pattern58, that is, an upper layer interconnect pattern, can be definitelyformed.

[0054] In this manner, according to the fabrication method of Embodiment1, the dummy pattern 53 b including the air gaps 73 between plural finepatterns can be definitely formed in a pattern region where the firstinterconnect pattern 53 a is comparatively sparse in the semiconductordevice.

[0055] Also, since the second insulating film 57 with high directivityis used for forming the air gaps and the third insulating film 58 withlow directivity is used for forming the interlayer insulating film inthis embodiment, the controllability in the positions of the tops of theair gaps 72 and 73 can be improved. In addition, even when theinterconnects are formed at comparatively large spacing, the air gaps 72and 73 can be definitely formed. The interlayer insulating film may beformed from a single-layer insulating film, and in this case, a siliconoxide film with relatively low coverage is preferably used as theinterlayer insulating film.

[0056] Although the two-level interconnect structure including the firstinterconnect pattern 53 a and the second interconnect pattern 59 isformed in this embodiment, the number of the interconnect layers is notlimited to two. Any multi-level air gap interconnect structure includingthree or more layers can be formed by forming a dummy pattern similar tothe dummy pattern 53 b in a pattern region where the second interconnectpattern 59 is comparatively sparse.

[0057] In order to increase the size of the air gap 73 of the dummypattern 53 b, the spacing 30 b of the dummy pattern 30 shown in FIG. 1Bis preferably set to 0.75 μm or less.

[0058] Embodiment 2

[0059] A method for fabricating a semiconductor device according toEmbodiment 2 of the invention will now be described with reference tothe accompanying drawings.

[0060]FIGS. 4A through 4C, 5A through 5C and 6A through 6C arecross-sectional views for showing procedures in the method forfabricating a semiconductor device including an air gap dummy patternaccording to Embodiment 2.

[0061] In Embodiment 2, an interconnect pattern does not include airgaps, and a plug for electrically connecting a lower layer interconnectpattern to an upper layer interconnect pattern is formed after formingthe lower layer interconnect pattern and a dummy pattern.

[0062] First, as shown in FIG. 4A, an underlying insulating film 62 ofsilicon oxide is deposited all over an interconnect region on asemiconductor substrate 61 of silicon by, for example, the plasma CVD.Thereafter, a first interconnect pattern forming layer 63 of aluminumalloy is deposited all over the underlying insulating film 62 by, forexample, the sputtering.

[0063] Next, as shown in FIG. 4B, a resist pattern 71A for a firstinterconnect pattern and a resist pattern 71B for a dummy pattern areformed on the first interconnect pattern forming layer 63 by thephotolithography. By using the resist pattern 71A for a firstinterconnect pattern and the resist pattern 71B for a dummy pattern as amask, the first interconnect pattern forming layer 63 is etched. Thus, afirst interconnect pattern 63 a and a dummy pattern 63 b electricallyinsulated from the first interconnect pattern 63 a and including threefine patterns each having a stripe plane shape and spaces 63 d betweenadjacent fine patterns are formed from the first interconnect patternforming layer 63.

[0064] Then, as shown in FIG. 4C, after removing the resist patterns 71Aand 71B, a first insulating film 64 of silicon oxide for forming airgaps is deposited all over the semiconductor substrate 61 including thefirst interconnect pattern 63 a and the dummy pattern 63 b by the plasmaCVD using a monosilane (SiH₄) gas and a dinitrogen monoxide (N₂O) gas.At this point, the first insulating film 64 is preferably formed from afilm with low coverage and high directivity. When such an insulatingfilm with low coverage is used, the deposited first insulating film 64overhangs like a peak on the top portions of the adjacent fine patternsof the dummy pattern 63 b, and hence, air gaps can be definitely formedbetween the fine patterns.

[0065] Thereafter, as shown in FIG. 5A, a second insulating film 65,which may be an insulating film with comparatively high coverage, ofsilicon oxide to be used as an interlayer insulating film is depositedall over the semiconductor substrate 61 including the first insulatingfilm 64 by the high density plasma CVD. Thus, air gaps 73 are formedbetween the fine patterns of the dummy pattern 63 b, and the dummypattern 63 b attains the air gap structure.

[0066] Since the dummy pattern 63 b thus includes a plurality of finepatterns and the air gaps 73 provided between the adjacent finepatterns, the second insulating film 65 is not filled in the air gaps 73of the dummy pattern 63 b. Therefore, a difference H1 in the absoluteheight becomes smaller than in the conventional dummy pattern includingno air gaps. As a result, the deposited second insulating film 65attains good planeness on its top face.

[0067] Next, as shown in FIG. 5B, the top face of the second insulatingfilm 65 is polished and planarized by the CMP. At this point, since thedifference H1 in the absolute height attained before the polishing issufficiently small, a difference H2 in the absolute height attainedafter polishing and planarizing the top face of the second insulatingfilm 65 is very small. Thus, a sufficiently planar face can be obtained.

[0068] Then, as shown in FIG. 5C, a resist film is applied on the secondinsulating film 65, and a mask pattern 75 for a plug having an opening75 a above the first interconnect pattern 63 a is formed by thephotolithography.

[0069] Subsequently, as shown in FIG. 6A, the second insulating film 65and the first insulating film 64 are etched by using the mask pattern 75for a plug, thereby forming a contact hole 65 a in the second insulatingfilm 65 above an interconnect of the first interconnect pattern 63 a.

[0070] Next, as shown in FIG. 6B, a conducting film of, for example,tungsten is deposited all over the second insulating film 65 includingthe contact hole 65 a by the vapor evaporation or the like, so as tofill the deposited conducting film in the contact hole 65 a.Subsequently, an excessive portion of the conducting film deposited onthe second insulating film 65 is polished and removed by the CMP,thereby forming a plug 66 of tungsten in the contact hole 65 a.

[0071] Then, as shown in FIG. 6C, a conducting film electricallyconnected to the plug 66 is formed on the planarized second insulatingfilm 65 by the sputtering or the like, and a second interconnect pattern67 is formed from the conducting film. At this point, since the secondinsulating film 65 is sufficiently planarized, the second interconnectpattern 67 is never disconnected owing to a level difference in thesecond insulating film 65. Thus, the second interconnect pattern 67,that is, an upper interconnect pattern, can be definitely formed.

[0072] In this manner, according to the fabrication method of Embodiment2, the dummy pattern 63 b including the air gaps 73 between a pluralityof fine patterns can be definitely formed in a pattern region where thefirst interconnect pattern 63 a is comparatively sparse in thesemiconductor device.

[0073] Also, since the first insulating film 64 with high directivity isused for forming the air gaps and the second insulating film 65 with lowdirectivity is used for forming the interlayer insulating film in thisembodiment, the controllability in the positions of the tops of the airgaps 73 can be improved. In addition, even when the spacing between thefine patterns of the dummy pattern 63 b is comparatively large, the airgaps 73 can be definitely formed. The interlayer insulating film may beformed from a single-layer film, and in this case, a silicon oxide filmwith relatively low coverage is preferably used for the interlayerinsulating film.

[0074] Although the two-level interconnect structure including the firstinterconnect pattern 63 a and the second interconnect pattern 67 isformed in this embodiment, the number of layers of the interconnects isnot limited to two. Any multi-level air gap interconnect structureincluding three or more layers can be formed by forming a dummy patternsimilar to the dummy pattern 63 b in a pattern region where the secondinterconnect pattern 67 is comparatively sparse.

[0075] In order to increase the size of the air gap 73 of the dummypattern 63 b, the spacing 30 b of the dummy pattern 30 shown in FIG. 1Bis preferably set to 0.75 μm or less.

What is claimed is:
 1. A semiconductor device comprising: a firstinterconnect pattern formed on a semiconductor substrate; and a secondinterconnect pattern formed above said first interconnect pattern withan interlayer insulating film sandwiched therebetween, wherein saidfirst interconnect pattern includes a dummy pattern electricallyinsulated from said first interconnect pattern, and said dummy patternincludes a plurality of fine patterns adjacent to each other and airgaps sandwiched between said adjacent fine patterns.
 2. Thesemiconductor device of claim 1, wherein air gaps are provided betweenadjacent patterns of said first interconnect pattern.
 3. Thesemiconductor device of claim 1, wherein said dummy pattern is formed ina region on said semiconductor substrate where said first interconnectpattern is relatively sparse.
 4. A method for fabricating asemiconductor device comprising: a first step of forming a firstinterconnect pattern forming layer from a conducting film on asemiconductor substrate and a first insulating film on said firstinterconnect pattern forming layer; a second step of forming a plugelectrically connected to said first interconnect pattern forming layerby forming an opening in said first insulating film by selective etchingand filling said opening with a conducting film; a third step of forminga resist pattern corresponding to a first interconnect pattern includinga dummy pattern from a resist film applied over said semiconductorsubstrate including said plug; a fourth step of patterning said firstinsulating film by etching said first insulating film with said resistpattern and said plug used as a mask; a fifth step of forming, from saidfirst interconnect pattern forming layer, said first interconnectpattern and said dummy pattern that is electrically insulated from saidfirst interconnect pattern and includes a plurality of fine patternsadjacent to each other by etching said first interconnect patternforming layer with said resist pattern and said plug used as a mask; asixth step of forming, on said semiconductor substrate, a secondinsulating film covering said plug, said first interconnect pattern andsaid dummy pattern so as to form air gaps between patterns of said firstinterconnect pattern and between said fine patterns of said dummypattern; and a seventh step of planarizing a top face of said secondinsulating film until said plug is exposed and forming, on said secondinsulating film, a second interconnect pattern electrically connected tosaid plug after planarization.
 5. The method for fabricating asemiconductor device of claim 4, wherein said first step includes asub-step of forming an underlying insulating film on said semiconductorsubstrate before forming said first interconnect pattern forming layer,and the method further includes, between said fifth step and said sixthstep, a step of trenching an upper portion of said underlying insulatingfilm by etching said underlying insulating film with said resist patternand said plug used as a mask.
 6. A method for fabricating asemiconductor device comprising: a first step of forming a firstinterconnect pattern forming layer of a conducting film on asemiconductor substrate; a second step of forming a resist patterncorresponding to a first interconnect pattern including a dummy patternfrom a resist film applied over said semiconductor substrate; a thirdstep of forming, from said first interconnect pattern forming layer,said first interconnect pattern and said dummy pattern that iselectrically insulated from said first interconnect pattern and includesa plurality of fine patterns adjacent to each other by etching saidfirst interconnect pattern forming layer with said resist pattern usedas a mask; a fourth step of forming, on said semiconductor substrate, aninsulating film covering said first interconnect pattern and said dummypattern so as to form air gaps between said fine patterns of said dummypattern; a fifth step of planarizing a top face of said insulating filmand forming a plug electrically connected to said first interconnectpattern by forming an opening in said insulating film afterplanarization by selective etching and filling said opening with aconducting film; and a sixth step of forming, on said insulating film, asecond interconnect pattern electrically connected to said plug.